2011/01/25 Duan add testing results of first ROACH crate
Method and Results
Summary of the test results:
• All 8 boards can be powered up and sucessfully loaded firmware!
• 2 boards show 1 clock cycle delay issue (can be
fixed by adjust buffer by 1 clock cycle); other 6 without any offset
between I and Q;
• The internal QDR random delay is common for all the
boards, that means the fix on FPGA will work on all the boards.
• All board show similar wired power level response: roach_crate_test_part1_powerLevel.pdf
• the reason I think it is not simply due to offset
between I and Q is because: 1. the roll off of IQ offset is more
linear. 2. when I try to put 1 clock cycle offset, I can clearly see
the response is offset, which looks like this:
a example of how it looks like when there is offset between I and Q but
we did not taken that into account: with_without_offset_powerlevel.pdf
Possible reason I can think of:
the fact that LPF somehow helps make me think the problem is aliasing
from high frequency (245Mhz - 490Mhz). but when we test IF board
before, we don't suffer from this a lot. (we might has such effect all
the time, just we didn't really pay attention because the ripple is
small). Might be mean there is coupling between the cables, or there is
feedback along the cable!!! we might need better isolation.
In summary, I think aliasing effect is the fundamental. we might have
such problem from long time ago (the reason I say this is the center
tones also shows some ripple and can not really explained by LPF or DAC
sinc roll off) but didn't pay attention.
The ripple is also looks like standing way inside the cable itself
(this might be the same thing as aliasing). So the SMA connectors might
be the reason?
mini-circuit LPF helps might because it introduce more insolation as well!!!
I looked the SMA cable data sheet online and measured the SMA cable in
lab, the attenuation for our frequency range is not a problem.
Possible way to make it work:
1. try new SMA cables with better isolation along cable; better cable to connector connection.
The performance test when all the board are loaded and running will be test.