2011/07/11 Duan

Abstract

Here is to summarize the current status of readout electronics and some problem we met duing system integration.

Motivation

To keep track each problem for current readout.

Method and Results

•    Two DAC chip not start together:

◦    By load same buffer for TWO DAC chips (DAC_I and DAC_Q), we find there is certain amount of phase delay between the two chips. And such delay going to introduce us problem like this: DAC_IQ_Phase_mismatch.pdf

    solution: we implement the detect phase of DAC feature for the firmware, and tune the phase for DACs each time we turn on electronic from power off

•    Missing package: we took 8 hours data with 1G ethernet and find the time stamp for data is:

◦    timestamp_8hour.pdf timestamp_diff_8hour.pdf
◦    We are missing 0.011% of data package (data package at 100Hz rate).

    solution: 1. Small package size. 2. Take raw data and format them to .nc formart in Matlab, instead of doing it on Python directly.