2010/01/16 Duan
2010/01/23 Duan: Update some software corresponding to the firmware v2
2010/02/13 Duan: Update Test results of new Firmware and New ADC/DAC board Part 1
2010/02/20 Duan: Update on new Firmware(decimation design) and New ADC/DAC board(the problem we saw during lab testing)
2011/02/27 Duan: Updata on simulation of decimation on FPGA (FIR or coaddition or 2 stage FIR)
2011/03/06 Duan: Updata simulation of decimation with real astronomy data.
2011/03/19 Duan: update Test New ADC/DAC board with Heatsink and External DC power on the board with internal loop
2011/03/21 Duan: update the decimation analysis for Band 3
2011/05/04 Duan: update the measurement results of V2 firmware with FIR added
2011/05/30 Duan: add the software for IF board control in Matlab
2011/08/09 Duan: add solution and discussion about FIR reorder problem

Abstract

Purpose of the log is to:

1. Explain in detail of all the software below or point to the note to explain it:
•    a.FPGA Firmware 2.0 version
     b.Software associate with the FPGA firmware 

     c.GUI interface and software associate with CSO telescope 

     d.Normal Observation User manual 

     e.Software associate with output data

2. To serve as part of the CSO MUSIC telescope User’s Manual for future observer and future software developer.

3. To document and archive all the software (include all the matlab, python, c, xilinx, IDL etc) related to readout system.

Why

We haven't systematically organize all the software related to the readout system yet; We will need this document for future developer and MUSIC user at CSO.

How

Introductory and overview notes for software (incomplete): FPGA_Model_Firmware_Version_2_modify3.pdf

TESING Reports:

•    Test of 2nd Generation of FPGA Firmware and 2nd Generation of ADC/DAC Board:

Test_of_Second_Generation_of_Firmware_Part_1.pdf
Detailed noise plots:
New_FIrmware_New_ADCDAC_Test_ALL.pdf

Update on newADC/DAC and firmware(20 Feb, 2011): Update_of_newBoard_newFirmware_20Feb.pdf

Update on FPGA firmware design: about decimation design (27 Feb, 2011) : FPGA_firmware_version_2_Decimation.pdf , test_FIR_FIR_business_compare_Vacc.m

Update on FPGA firmware design: Apply decimation design with real astronomy data(5 mar, 2011) :

•    Original Data from Jack: data.zip , Readme_about_the_data_file_name.pdf
     Results of the data go through the different decimation design:
      readme_about_following_noise_plots.pdf , matlab_code.m 


A typical audio stream/spectrum from Jack's data at 300Hz without any modification:
  typical_audio_stream_300Hz.pdf , typical_20log_spectrum_300Hz.pdf , typical_loglog_spectrum_300Hz.pdf

The results of data go through different decimation method (21 Mar, 2011 updated):

1.    20100624_b3_x0_y0_time_stream.pdf
2.    20100624_b3_x0_y0_time_difference_divide_peak_of_time_stream_of_method_1_linear.pdf
3.    20100624_b3_x0_y0_time_difference_divide_peak_of_time_stream_of_method_1_semilogy.pdf
4.    20100624_b3_x0_y0_frequency_domain.pdf
5.    20100624_b3_x0_y0_frequency_domain_difference_diveide_peak_of_method_1_linear.pdf
6.    20100624_b3_x0_y0_frequency_domain_difference_diveide_peak_of_method_1_semilogy.pdf

New ADC/DAC board testing update(14 Mar, 2011):

•    There is NO difference with or without heatsink on the ADC chip for the new ADC/DAC board. the 1/f noise test is exactly same as "Test_of_Second_Generation_of_Firmware_Part_1.pdf" For the test with external power(just one board done the external power configration, will make change on the other one): NewADCDAC_ext_Power.pdf

New ADC/DAC board testing update(19 Mar, 2011):

•    We put on new Heatsink, New Al Plate, and optional a Fan blow air on top of ADC/DAC board; we also try to use regulated external DC power supply for the new ADC/DAC board (for the old ADC/DAC, the DC power is come from ROACH through Z-Dok; in the new ADC DAC board, we leave the optional to switch between ROACH’s Power or External Power):

 New_ADCDAC_NewFirmware_Ext_Power_Regulator_update_19Mar2011.pdf

New firmware with FIR added (4th May, 2011):

•    We use cascaded two FIR design in FPGA and test with DAC loop back to ADC.
The expected SNR is 10*log10( 10(6.1) * 2(16) * 75 ) = 127.9 dB :
 Firmware_V2_Test_with_Cascaded_FIR.pdf
Firmware_V2_without_FIR: NewADCDAC_ext_Power.pdf

Firmware_V1 noise results: http://www.submm.caltech.edu/wiki/kids//DesignLog133/attachments/MUSIC_Readout_Test_Noise_Part_2.pdf

Software Update

Firmware V2 development Log(till 23thJan,2010): fpgafirmwareV2_design_log.txt

Actual Firmware V2 (still working on the final one):
Matlab and Python for Firmware V2(under testing): software_for_firmwareV2.zip
Matlab IF board control software(30 May, 2011): Matlab_IF_board_code.zip

FPGA firmware's FIR output order
FIR_output_order_discussion.pdf