Abstract

the VCO will be used on IF board to provide LO for both up and down IQ Mixers.
This is a summary of Readout system phase noise test, by comparing the VCO or off-the-shelf Synthesizer serving as Mixer's LO.

Why

We will use VCO as mixer's LO on the IF board. (We might also use VCO as clock for ADC/DAC if we don't use external clock). From circuit simulation software(page 3-4 in 1overf note below), VCO should has similar phase noise performance as our Synthesizer at 3 GHz range with offset 0.1 Hz to 100Hz (not very good for offset freuquency above 1KHz); and its performance will not as good as Synthesizer at baseband freqeuncy. (details can be found in the reference below and desgin log 104)

VCO datasheet doesn't provide enough phase noise information down to offset 0.1 Hz.
So we tested VCO chip in lab to compare its performance with Synthesizer at IF band.
We will also try to test VCO serve as clock signal for ADC and DAC boards.

How

•    Setup:

◦    DAC + IQ_Up (IQ0255M) + digital attenuator + IQ_down(IQ0255L)+BB_Amp+ADC DAC generated 126 carriers comb signal; channelizing firmware running on ROACH 
Driving two IQ mixers with either synthesizer or VCO: 
With Synthesizer: use synthesizer MG3690 (0-40GHz), with frequency 3.22GHz and power 20dBm at input of splitter; 
With VCO: VCO+ IF_Amp (ZVA183S+); VCO output is -1dBm and 3.22 GHz; power 20dBm at input of splitter.

•    Test:
◦    Run whole readout system and record data for 10mins for both VCO LO and Synthesizer LO, with attenuator set to 0,4,8,16 dB.

•    Results
◦    Rotate the received 100Hz data stream into amplitude and phase direction, and analyze the phase information Terminate the input to the IQ down converter, and get noise floor : noise_floor_freq_phase.pdf , noise_floor_time_phase.pdf

◦    Compare VCO & Synth Phase noise v.s. difference input power(attenuator setting)
    0dB attenuator : 0dB_freq.pdf , 0dB_time.pdf , 0dB_power.pdf
    4dB attenuator : 4dB_freq.pdf , 4dB_time.pdf , 4dB_power.pdf 

    8dB attenuator : 8dB_freq.pdf , 8dB_time.pdf , 8dB_power.pdf
    16dB attenuator : 16dB_freq.pdf , 16dB_time.pdf , 16dB_power.pdf

◦    Compare Phase noise of VCN & Synth for 10 different resonator with fixed attenuator setting 0dB: 0dB_10_resonators.pdf

◦    Average VCO phase noise v.s. different input power(attenuator setting)
        VCO_Power_level.pdf , VCO_Time_Phase.pdf , VCO_freq_phase.pdf

◦    Average Synthesizer phase noise v.s. different input power(attenuator setting)
        Synth_Power_level.pdf , Synth_Time_Phase.pdf , Synth_freq_phase.pdf

◦    Median Allan Variance as a function of carrier power for Synthesizer and VCO
        Median_Allan_Variance_126_Carriers_Synth_vs_VCO.pdf

◦    Allan Variance fits and PSDs as a function of carrier power
       Allan_Variance_White_Noise_Amplitude.pdf,
       Allan_Variance_OneOverF_Amplitude.pdf,
       OneOverF_Power_Comparison_Random_Carriere.pdf,
       PSD_Random_Carrier.pdf, Allan_Variance_Random_Carrier.pdf


Conclusions:

◦    Using VCO or Synthesizer as Mixer’s LO results in same performance for MUSIC readout system 
Possible reasons are:
         From the simulation of VCO phase noise, at 3GHz, it is phase noise is quite similar to the synthesizer we have. 
b. Noise are cancelled by each other during up and down converting

◦    There is storing relation between phase noise and input power to ADC. 
Possible reasons are:
    The simple rotation is not optimal for separate phase noise, the noise behavior may partially come from amplitude 1/f noise 
b. Need to take into account the cable delay and other component in the whole signal chain to better separate phase noise. 
c. The jitter of ADC board might related to the signal power level, and those clock jitter will results in phase noise.

◦    For a fixed input power level setting (attenuator setting), phase noise has small variance across 126 resonators. This should due to the fact that power levels for 126 carriers are very different (+/-10dB). But this may not exactly same as situation in the above item #2. Could there also be some effect from FPGA firmware due to the cascaded 2 FFT desgin??( Will use matlab to simulation this part).


Things need to be done:

◦    Confirm the phase noise level in the LUT generated from DAC; Compare the performance of buffer without avoid clipping adjustment; compare the performance for equal signal power for all resonator
◦    Confirm the phase noise performance from cascaded 2 FFT, Is there any effect on phase noise
◦    Make test for VCO serve as clock of ADC/DAC

Reference about phase noise:

◦    VCO, Synthesizer phase noise and jitter: ADF4350.pdf , CG635.pdf , MG3690.pdf , SIM940c.pdf
◦    Jitter (either clock to aperture) to phase noise: http://www.jittertime.com/resources/pncalc.shtml ADC jitter : ads5463.pdf
A software used to simulate phase lock loop circuit (e.g. VCO): http://www.analog.com/pll Phase noise, frequency noise, TLS noise of device, electronics: Study_of_1overf_noise_in_IF_system_v3.pdf